1. Field of the Invention
The present invention relates to a range selectable address decoder and a frame memory device for processing graphic data at high speed using the same, and more particularly, to a range selectable address decoder and a frame memory device using the same for processing graphic data at high speed, in which row/column address decoders capable of designating addresses of a desired range by two addresses are used, to thereby select a number of memory cells of a desired range all at a time and write data in the selected memory cells.
2. Description of the Related Art
In general, a portable terminal having a processor having a data processing capacity lower than a general purpose personal computer (PC) such as a mobile communications terminal or a personal digital assistant (PDA) which will be referred to as a portable terminal, requires a high speed signal processing technology for processing graphic data at high speed, in order to display animation images, games or advertises using graphic data on a display such as a liquid crystal display (LCD).
In particular, LCD panels are changed from super twist nematic (STN) to thin film transistor (TFT) and an organic electroluminescent (EL) display capable of performing a signal response faster than a TFT LCD is under development. Also, a portable terminal adopts functions of processing various kinds of sounds such as a 40-chord bell sound function and various kinds of images taken by a 300,000-pixel digital camera. In contrast, the size of the portable terminal becomes more compact. Thus, the portable terminal confronts a double difficulty that should embody a high-speed signal processing within a limited space.
Thus, such a portable terminal requires a system that a processor to be mounted for processing signals should operate at high performance without having much burden when performing a high-performance signal processing.
Meanwhile, when video signals are displayed on a display such as an LCD of a conventional portable terminal, graphic data is temporarily written in a frame memory device formed of RAMs according to designation of addresses by the processor (a host), and then data is read from the frame memory device to be displayed on a display.
A general memory device, i.e., RAMs that are used in a frame memory device has a structure of writing only single data with respect to a single address, becomes an obstacle in processing graphic data at high speed, and imposes a heavy burden on a processor.
That is, as shown in FIG. 1, a conventional RAM having the above-described structure includes a column address decoder 2 for selecting a column address with respect to a number of memory cells 1 that are aligned in a matrix form, and a row address decoder 3 for selecting a row address with respect to the number of memory cells 1. In such a RAM, one column address and one row address are applied to the column address decoder 2 and the row address decoder 3, to thereby enable one memory cell to be selected to perform a write operation in order to store input data.
Here, it is assumed that a conventional graphic processing method is a case of drawing a straight line that is formed by column addresses of 1 to 100 for a certain row address. That is, in the case that row address values are the Y-axis values on a screen and column address values are the X-axis values on the screen, the straight line means a line parallel with the X-axis. Thus, a memory adopting a conventional single memory cell designation method should execute memory write operations one-hundred times in order to draw a single straight line. Accordingly, the above-described conventional technology need to be improved inevitably in order to process graphic data at high speed.
Further, in order to draw a rectangle that is formed of row addresses of 1 to 100 and column addresses of 1 to 100, the conventional technology should perform memory write operations 100×100, that is, 10,000 times. As a result, a graphic data processing speed is slow and a burden to be imposed on a processor due to the above-described repeated write operations increases, in the conventional technology.
A technique for writing data into memory cells by memory cell block unit is disclosed in PCT International Publication Gazette No. WO 96/36052. In this prior art, it is impossible to designate a number of memory cells by user's desired pattern at a time so as to write graphic data into the number of designated memory cells.